1. Field of the Invention
The present invention relates to a solid-state imaging device that has an A/D conversion function of converting an analog pixel signal output from a pixel into digital data.
Priority is claimed on Japanese Patent Application No. 2011-236021, filed on Oct. 27, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
As an example of an A/D conversion circuit used in an existing solid-state imaging device, a configuration shown in FIG. 15 (for example, see Japanese Unexamined Patent Application, First Publication No. 2009-38726 and Japanese Unexamined Patent Application, First Publication No. 2009-38781) has been known. First, a configuration of an A/D conversion circuit shown in FIG. 15 will be described. The A/D conversion circuit shown in FIG. 15 includes a delay part 101, a comparison circuit 102, a latch part 103, a counter circuit 104, and a buffer circuit 105.
The delay part 101 has a plurality of delay units DU[0] to DU[7] that delay and output input signals. To the leading delay unit DU[0], a start pulse φStartP is input. To the comparison circuit 102, an analog signal φSignal that becomes a target from which a time is detected and a ramp wave φRamp that decreases with the elapse of time are input. The comparison circuit 102 outputs a signal φCO that represents a result of a comparison between the analog signal φSignal and the ramp wave φRamp. The latch part 103 has latch circuits L_0 to L_7 that latch logic states of output signals φCK0 to φCK7 of the respective delay units DU[0] to DU[7] in the delay part 101. The counter circuit 104 performs counting based on the output signal φCK7 of the delay unit DU[7] in the delay part 101.
By the comparison circuit 102, a time interval (size in a time-axis direction) in accordance with an amplitude of the analog signal φSignal is generated. The buffer circuit 105 is an inverting buffer circuit that inverts and outputs an input signal. To facilitate understanding of the description, the buffer circuit 105 is constituted as an inverting buffer circuit.
When an output signal φHold of the buffer circuit 105 is high, the latch circuits L_0 to L_7 constituting the latch part 103 are in an enable (valid) state and output the output signals if φCK0 to φCK7 of the delay units DU[0] to DU[7] as they are. When the output signal φHold of the buffer circuit 105 changes from High to Low, the latch circuits L_0 to L_7 are placed in a disable (invalid) state and latch logic states in accordance with the output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] of the time.
In addition, a count latch circuit that latches a logic state of a count result of the counter circuit 104 is not specified, but a counter circuit having a latch function is used, such that the counter circuit 104 also serves as the count latch circuit.
Next, operation of the existing example will be described. FIG. 16 illustrates operation of the A/D conversion circuit according to the existing example. First, at a timing (first timing) related to the start of comparison by the comparison circuit 102, a clock having a period that approximately coincides with a delay time of the delay part 101 (the sum of delay times of the eight delay units DU[0] to DU[7]) is input to the delay part 101 as the start pulse φStartP. In this way, the delay part 101 starts operation. The delay unit DU[0] constituting the delay part 101 delays the start pulse φStartP and outputs as the output signal φCK0. The delay units DU[1] to DU[7] constituting the delay part 101 delay output signals of delay units in their front stages and output as the output signals φCK1 to φCK7. The output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] are input to the latch circuits L_0 to L_7 of the latch part 103. The latch circuit L_7 outputs the input output signal φCK7 of the delay unit DU[7] to the counter circuit 104 as it is.
The counter circuit 104 performs a count operation based on the output signal φCK7 of the delay unit DU[7] output from the latch circuit L_7 of the latch part 103. In this count operation, a count value increases or decreases with rise or decay of the output signal φCK7. At a timing (second timing) at which the analog signal φSignal and the ramp wave φRamp approximately coincide with each other, the output signal φCO of the comparison circuit 102 is inverted. Also, at a timing (third timing) after a predetermined delay time given to an input signal in the buffer circuit 105 elapses, the output signal Hold of the buffer circuit 105 becomes Low.
In this way, the latch circuits L_0 to L_7 are placed in the disable state. At this time, logic states in accordance with the output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] are latched in the latch circuits L_0 to L_7. The latch circuit L_7 stops operation, and thereby the counter circuit 104 latches the count value. From the logic states latched by the latch part 103 and the count value latched by counter circuit 104, digital data corresponding to the analog signal φSignal is obtained.
By the A/D conversion circuit according to the existing example, digital data corresponding to a time interval in accordance with a voltage of the analog signal φSignal is obtained. In other words, digital data corresponding to the analog signal φSignal is obtained.
In the existing A/D conversion circuit, the latch circuits L_0 to L_7 constituting the latch part 103 operate for the period of the time interval, and thus a current value consumed by the latch part 103 becomes large.
In the A/D conversion circuit of the existing example, the latch circuits L_0 to L_7 constituting the latch part 103 continuously operate for a period of time from the first timing to the third timing. The output signals φCK0 to φCK7 of the delay part 101 have high frequencies in general. For this reason, the current value consumed by the latch part 103 becomes high due to current consumed by the latch circuits L_0 to L_7 constituting the latch part 103.
Here, as an example of a concrete device used in the A/D conversion circuit of the existing example, an imager used in a digital still camera (DSC) and the like is considered. Specifically, it is assumed that specifications are the number of pixels of 20,000,000 and a frame rate of 60 frame/sec. The A/D conversion circuit is disposed in every pixel column. To facilitate description, an arrangement of the 20,000,000 pixels is assumed to be 4000 rows×5000 columns vertically and horizontally, and to further facilitate description, it is assumed that there is no blanking period. Then, the number of rows that read a pixel signal per second becomes is described below.60 frame/sec×4000 row/frame=240 Kline/sec
In other words, the read rate for one row becomes 240 KHz. For example, assuming that AD conversion of 10 bits is configured with upper seven bits (the count value of the counter circuit 104) and lower three bits (the data of the latch circuits L_0 to L_7 constituting the latch part 103), the output signals φCK0 to φCK7 are necessary to be output from the delay part 101 at 128 (=27) times the read rate for one row, in other words, at about 30 MHz. Here, assuming that a current consumption value per one latch circuit constituting the latch part 103 is 1 μA/latch circuit, a current consumption value of the latch circuits L_0 to L_7 per one column is 1 μA/latch circuit×8 latch circuits=8 μA.
That is, a current consumption value of the 5000 columns becomes 40 mA. Since, in this calculation, a period for which a comparison operation is not possible as AD conversion, such as a standby period until the A/D conversion circuit receives data from a pixel, and the like, is not taken into consideration, and also a period for reading a pixel signal from an Optical Black (OB) pixel other than the pixels or a blanking period is excluded, it is considered in practice that a frequency becomes higher than the frequency of 30 MHz estimated as mentioned above.